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Jetson Customize Usb

NVIDIAOfficialCreated by Jetson TeamDistributed by NVIDIA

  • Skill
  • Workflow
  • Cloud and DevOps
  • Apache-2.0
  • Medium risk
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From the author

Enable/disable Jetson USB2/USB3 SS ports via kernel-DT overlay. Do NOT use for UPHY lane allocation or ODMDATA edits.
— the description by Jetson Team

AutoGineer summary

Written by AutoGineer from the skill’s own files, not by the author

The jetson-customize-usb skill enables, disables, or modifies the role of USB2 and USB3 SuperSpeed (SS) ports on Jetson Thor and Orin platforms. It ensures that port configurations—including wiring, VBUS-EN, OC, CC GPIOs, and UPHY lane assignments—are correctly reflected in the kernel device tree. The skill enforces a strict three-place lockstep update pattern (lane status, port status, and host xHCI phys-list) to prevent host controller crashes and ensures that all modifications are rendered as a self-contained kernel-DT overlay within the BSP source repository.

What it does

  • Enables or disables USB2 and USB3 SS ports via kernel-DT overlays.
  • Configures port roles, VBUS-EN, OC, and CC GPIOs based on carrier schematics.
  • Maintains a three-place lockstep update for lane, port, and host xHCI controller bindings.
  • Resolves companion links between USB2 and USB3 SS ports to prevent driver errors.
  • Validates configurations against carrier pinmaps and schematic documentation.
  • Generates a commit-ready kernel-DT overlay for the BSP source repository.

When to use it

  • When you need to enable or disable USB ports on a custom Jetson carrier board.
  • When a USB receptacle fails to enumerate after flashing the device.
  • When you need to configure USB roles or wiring for specific carrier hardware.
  • After running jetson-customize-uphy to ensure USB3 SS port settings align with new lane allocations.

Advantages

  • Prevents common host xHCI controller crashes through strict lockstep enforcement.
  • Ensures hardware-software alignment by requiring carrier schematic and pinmap verification.
  • Automates complex device tree fragment generation for USB port topology.
  • Maintains system stability by preventing invalid port or lane configurations.

Usage examples

“Enable the USB3 SS port 2 on my custom carrier board.”
The agent will verify the carrier schematic, check the UPHY lane allocation, and generate a kernel-DT overlay that correctly enables the lane, port, and xHCI phys-list.
“Disable the USB hub connected to the carrier.”
The agent will identify the associated USB2 and USB3 SS ports, perform the companion cascade, and update the device tree to safely disable the entire hub topology.

Install

  1. Download the skill as a ZIP:

    https://autogineer.com/agent-skills/nvidia/jetson-customize-usb/download

  2. Unzip it into the cross-client skills folder of your project:

    mkdir -p .agents/skills && unzip jetson-customize-usb.zip -d .agents/skills

Documentation by Jetson Team

Customize USB (per-port enable / disable / role)

Purpose

Enable, disable, or change the role of USB2 / USB3 SS ports on a Jetson Thor (Tegra264) or Orin (Tegra234) custom carrier. Captures per-port wiring (role, max speed, VBUS-EN / OC GPIOs, CC1/CC2 GPIOs for Type-C, USB3 SS UPHY lane), resolves the SS to USB2 companion graph from the in-tree DTB, then renders a self-contained kernel-DT overlay that flips every port action in three places in lockstep (lane status, port status, host xHCI phys + phy-names).

UPHY lane allocation belongs to jetson-customize-uphy. No ODMDATA edit. Output is one commit to the composite custom overlay .dts in the bsp_sources/ hardware repo.

Prerequisites

  • Active profile with reference_devkit: + custom_carrier: blocks.

  • <source.root_path>/Linux_for_Tegra/.git exists (/jetson-init-source).

  • /jetson-derive-carrier has run — carrier flash-conf fork in the overlay tracker.

  • /jetson-customize-uphy has run when any enabled USB3 SS port needs a non-stock UPHY lane allocation. Its JSON sidecar at <workspace>/target-platform/<profile-stem>.jetson-customize-uphy.json is consulted for SS lane allocation.

  • Source-of-truth docs: Adaptation Guide §"Port the Universal Serial Bus", Module Design Guide §USB, SoC TRM (xusb block).

  • When custom_carrier: is present, both documents.custom_carrier_schematic AND documents.custom_carrier_pinmux_xls are REQUIRED. Refuse the run if either is missing — per-port routing (VBUS-EN / OC / CC GPIOs, SS lane wiring, hub fan-out) on a custom carrier cannot be guessed. Reference-devkit-only profiles skip this check.

  • dtc, fdtoverlay on PATH.

Overview

USB on Tegra spans three IP surfaces: the xusb_padctl block (USB2 OTG + USB3 SS PHYs), the tegra-xusb xHCI host controller, and an optional tegra-xudc device controller attached to the single OTG-capable USB2 port (usb2-0).

A per-port flip MUST touch three kernel-DT places in lockstep. Anything less crashes the host xHCI probe and leaves lsusb empty on every port (collateral damage to stock-okay ports):

#PlacePathWhat it controls
1Lane (PHY provider)xusb_padctl/pads/usb<2|3>/lanes/usb<2|3>-NSS / OTG PHY hardware-binding. status="disabled" then lane stops providing a PHY.
2Port (controller-binding)xusb_padctl/ports/usb<2|3>-NPer-port mode (host/device/otg), companion link, VBUS / OC / CC pin refs. status="disabled" then port removed from user-facing topology.
3Host xHCI phys-listbus@0/usb@<addr>.phys + .phy-namesArray of phandles + names the xHCI driver iterates. A ref to a disabled PHY returns -ENODEV and aborts the whole host probe.

NVIDIA's stock-disabled usb3-3 in the Thor base DTB is the canonical pattern — all three places flipped in lockstep.

Two extra rules ride on top of the three-place pattern:

  • Rule A — lane + port pairing. Lane (place 1) and matching port (place 2) MUST flip together.

  • Rule B — companion cascade. xusb_padctl/ports/usb3-N.nvidia,usb2-companion references a USB2 port phandle. Disabling that USB2 without cascading to its SS companion then tegra-xusb: failed to enable PHYs: -19.

Agentic, not table-driven — every port, controller, lane, companion link, phandle, and __symbols__ lookup is resolved at runtime from docs + DTB + carrier pinmap + schematic.

When to invoke

  • The user says "enable USB", "disable USB hub", "configure USB3 SS", "set USB role", "wire VBUS-EN", "tegra-xusb / xudc / dr_mode", or asks to bring up / take down a USB controller on a custom carrier.

  • A USB receptacle on the carrier doesn't enumerate after flash, OR collateral USB damage (lsusb empty after a previous jetson-customize-usb attempt) needs to be fixed.

  • jetson-customize-uphy re-allocated UPHY lanes affecting USB3 SS ports and per-port DT now needs to follow.

Procedure (summary)

The full step-by-step procedure lives in references/procedure.md.

  1. Step 1 — resolve active target + open source-of-truth docs.

  2. Step 2 — build the USB topology + companion graph from the in-tree DTB.

  3. Step 3 — AskUserQuestion for port(s) to enable / disable; surface companion cascade + on-carrier hub fan-out explicitly.

  4. Step 4 — per-port verify (module + carrier + UPHY lane) and capture wiring (VBUS-EN / OC / CC GPIOs via pin_verifier.py).

  5. Step 5 — render the kernel-DT overlay using the three-place pattern, append fragments (usb:padctl, usb:xhci, optional usb:xudc) to the composite custom overlay .dts, run fdtoverlay + the three post-merge invariants, commit to bsp_sources/.

  6. Step 6 — write run-state JSON sidecar (shape in references/run-state-sidecar.md), emit headline, then drive the downstream next-step chain via sequential AskUserQuestion prompts per references/procedure.md Step 6. Never substitute a printed "Next step: …" line for the prompts.

See references/gotchas.md for the load-bearing failure modes.

Limitations

  • Owns kernel-DT overlay only. ODMDATA does not expose a per-port USB status knob; do not edit it.

  • Does NOT allocate UPHY lanes — jetson-customize-uphy owns that. Refuse to commit an SS-enable until uphy run-state shows the lane allocated.

  • Does NOT directly patch the pinmux DTSI — routes SFIO mismatches to /jetson-customize-pinmux set-pin.

  • Does NOT compile the .dtbo or register OVERLAY_DTB_FILE+= — /jetson-build-source owns build + flash-conf registration.

  • Tegra platform invariant: only usb2-0 is OTG-capable; xudc attaches there only. All other USB2 ports and all USB3 SS ports are host-only.

Troubleshooting

  • Empty lsusb on every port, USB-eth at 192.168.55.1 still up: host xHCI bailed; three-place lockstep was broken. Inspect merged DTB; verify post-merge invariants in references/procedure.md Step 5d.

  • tegra-xusb: failed to enable PHYs: -19: companion cascade (Rule B) violated — a USB2 was disabled without its SS companion.

  • no port found or Requested PHY is disabled: Rule A violated — lane status and port status are mismatched.

  • FDT_ERR_NOTFOUND from fdtoverlay: a fragment used target = <&label> for a node whose label is not in __symbols__ (typical for host xHCI / tegra-xudc). Switch to target-path = "/bus@0/usb@<addr>".

  • dtc warning phys_property: cell 0 is not a phandle reference: benign; expected when using raw integer phandles in the host phys override.

  • Port boots but VBUS never asserts: vbus-supply references a regulator parent node that does not exist. Ensure the fixed regulator node is present before referencing it.

  • xHCI binds the wrong port at boot: host phys element order was not preserved. Only elide disabled entries; never reorder kept ones.

References

  • references/procedure.md — full step-by-step procedure.

  • references/gotchas.md — load-bearing failure modes.

  • references/run-state-sidecar.md — run-state JSON shape.

  • references/usb-architecture.md — Tegra USB IP architecture notes (xusb_padctl, tegra-xusb, xudc).

  • references/usb-dt-bindings.md — USB DT binding cheatsheet (lane / port / phys-list shapes).

  • ../../scripts/pin_verifier.py — shared HSIO pin verifier.

  • ../../references/platform_template.yaml — documents: block consumed by Step 1.

  • ../../context/bsp-customization-workflow.md — overlay edit protocol.

  • ../../references/bsp-customization-kernel-dtb.md — composite overlay append protocol.

  • ../jetson-customize-uphy/SKILL.md — sibling skill that owns UPHY lane allocation.

  • ../jetson-customize-pinmux/SKILL.md — sibling skill for VBUS-EN / OC / CC SFIO fixes.

  • ../jetson-derive-carrier/SKILL.md — must run first.

  • ../jetson-init-source/SKILL.md — produces the overlay tracker

    • bsp_sources repo.

Files

references/README.md

/jetson-modify-usb references

FilePurpose
usb-architecture.mdTegra USB block model: USB2 OTG ports, USB3 SS instances, UPHY lane pool, padctl assignments.
usb-dt-bindings.mdtegra_xusb / xudc / xusb_padctl DT bindings the agent emits in the overlay.

The skill is agentic — AskUserQuestion payloads are built on the fly from the per-port diff in step 2 of SKILL.md, not from a static questions.json. The Adaptation Guide §"Port the Universal Serial Bus" (URL pinned to session.adaptation_guide_version) is the authoritative source for every option, mode constraint, and per-port capability the agent surfaces.

Requirements and compatibility

Written for: Claude Code

Works with: Claude Code, Claude apps, OpenAI Codex, GitHub Copilot, Cursor, Gemini CLI, Kiro, OpenCode, Goose, Amp, Roo Code, JetBrains Junie, Factory Droid, Devin (ex-Windsurf), Mistral Vibe, OpenHands, Letta

“Works with” means the tool reads the open Agent Skills format; a skill written for one tool may use features others lack.

Needs: Names Claude Code tools, Needs Node.js

Security

What our scanner noticed· Medium risk

  • Large base64-encoded blobs

A static scan is not a guarantee. Skills are third-party content: review a skill before you let an agent use it.

Attribution and licence

Created by
Jetson Team
Publisher
NVIDIA (Official)
Distributed by
NVIDIA
Source
NVIDIA/skills · skills/jetson-customize-usb · commit fce3cca
Licence
Apache License 2.0 (redistribution allowed)
  • LICENSE (added by AutoGineer from LICENSE-APACHE)
  • ATTRIBUTION.md (written by AutoGineer)
Synced

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Download ZIP

The ZIP holds the skill’s files, its licence files and an ATTRIBUTION.md. Download jetson-customize-usb.zip